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1/17 april 2003 rev. 4.0 m48z129y* m48z129v 5.0v or 3.3v, 1 mbit (128 kb x 8) zeropower ? sram * contact local sales office features summary n integrated, ultra low power sram, power-fail control circuit, and battery n conventional sram operation; unlimited write cycles n 10 years of data retention in the absence of power n microprocessor power-on reset (reset valid even during battery back-up mode) n battery low pin - provides warning of battery end-of-life n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C m48z129y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v C m48z129v: v cc = 3.0 to 3.6v 2.7v v pfd 3.0v n self-contained battery in the caphat? dip package n pin and function compatible with jedec standard 128k x 8 srams figure 1. 32-pin pmdip module 32 1 pmdip32 (pm) module
m48z129y*, m48z129v 2/17 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . . 7 table 7. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. write enable controlled, write mode ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. chip enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v cc noise and negative going transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/17 m48z129y*, m48z129v summary description the m48z129y/v zeropower ? sram is a 1,048,576 bit non-volatile static ram organized as 131,072 words by 8 bits. the device combines an internal lithium battery, a cmos sram and a con- trol circuit in a plastic 32-pin dip module. the m48z129y/v directly replaces industry standard 128k x 8 sram. it also provides the non-volatility of flash without any requirement for special write timing or limitations on the number of writes that can be performed. figure 2. logic diagram table 1. signal names figure 3. dip connections ai02309 17 a0-a16 dq0-dq7 v cc m48z129y m48z129v g v ss 8 e w rst bl a0-a16 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable rst reset output (open drain) bl battery low output (open drain) v cc supply voltage v ss ground a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a16 rst v cc ai02310 m48z129y m48z129v 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 a12 a14 w bl 3 4 28 27 32 31
m48z129y*, m48z129v 4/17 figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 se conds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. ai03608 rst v ss voltage sense and switching circuitry 131,072 x 8 sram array a0-a16 dq0-dq7 e w g power v cc bl e internal battery symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage C0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
5/17 m48z129y*, m48z129v dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 5. ac testing load circuit note: 1. 50pf for m48z129v (3.3v). table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48z129y m48z129v unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai03630 c l = 100pf or 50pf (1) c l includes jig capacitance 650 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
m48z129y*, m48z129v 6/17 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. operation modes the m48z129y/v also has its own power-fail de- tect circuit. this control circuitry constantly moni- tors the supply voltage for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing data security in the midst of unpredictable system operation. as v cc falls, the control circuitry automatically switch- es to the battery, maintaining data until valid power is restored. table 6. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 10, page 12 for details. sym parameter test condition (1) m48z129y m48z129v unit C70 C85 min max min max i li input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current outputs open 95 50 ma i cc1 supply current (standby) ttl e = v ih 74ma i cc2 supply current (standby) cmos e = v cc C 0.2v 43ma v il input low voltage C0.3 0.8 C0.3 0.6 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = C1ma 2.4 2.2 v mode v cc e g w dq0-dq7 power deselect 4.5 to 5.5v or 3.0to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/17 m48z129y*, m48z129v read mode the m48z129y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the unique address specified by the 17 ad- dress inputs defines which one of the 131,072 bytes of data is to be accessed. valid data will be available at the data i/o pins within t avqv (ad- dress access time) after the last address input signal is stable, providing the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access times (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for t axqx (output data hold time) but will go indeterminate until the next address access. figure 6. address controlled, read mode ac waveforms note: chip enable (e ) and output enable (g ) = low, write enable (w ) = high. figure 7. chip enable or output enable controlled, read mode ac waveforms ai02324 tavav tavqv taxqx data valid a0-a16 dq0-dq7 valid data valid ai01197 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a16 e g dq0-dq7 valid
m48z129y*, m48z129v 8/17 table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 5, page 5). symbol parameter (1) m48z129y m48z129v unit C70 C85 min max min max t avav read cycle time 70 85 ns t avqv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 35 45 ns t elqx (2) chip enable low to output transition 5 5 ns t glqx (2) output enable low to output transition 3 5 ns t ehqz (2) chip enable high to output hi-z 30 40 ns t ghqz (2) output enable high to output hi-z 20 25 ns t axqx address transition to output transition 5 5 ns
9/17 m48z129y*, m48z129v write mode the m48z129y/v is in the write mode whenever w (write enable) and e (chip enable) are ac- tive. the start of a write is referenced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write en- able prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx af- terward. g should be kept high during write cy- cles to avoid bus contention; although, if the output bus has been activated by a low on e and g a low on w will disable the outputs t wlqz after w falls. figure 8. write enable controlled, write mode ac waveform figure 9. chip enable controlled, write mode ac waveforms ai02382 tavav twhax tdvwh data input a0-a16 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai03611 tavav tehax tdveh data input a0-a16 e w dq0-dq7 valid taveh tavel twlwh tavwl tehdx teleh
m48z129y*, m48z129v 10/17 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 5, page 5). 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48z129y m48z129v unit C70 C85 min max min max t avav write cycle time 70 85 ns t av wl address valid to write enable low 0 0 ns t av el address valid to chip enable low 0 0 ns t wlwh write enable pulse width 55 65 ns t eleh chip enable low to chip enable high 55 75 ns t whax write enable high to address transition 5 5 ns t ehax chip enable high to address transition 15 15 ns t dvwh input valid to write enable high 30 35 ns t dveh input valid to chip enable high 30 35 ns t whdx write enable high to input transition 0 0 ns t ehdx chip enable high to input transition 10 15 ns t wlqz (2,3) write enable low to output hi-z 25 30 ns t avwh address valid to write enable high 65 75 ns t ave h address valid to chip enable high 65 75 ns t whqx (2,3) write enable high to output transition 5 5 ns
11/17 m48z129y*, m48z129v data retention mode with valid v cc applied, the m48z129y/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically deselect, write protecting itself when v cc falls between v pfd (max), v pfd (min) win- dow. all outputs become high impedance and all inputs are treated as dont care. note: a power failure during a write cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the rams content. at voltages below v pfd (min), the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z129y/v may re- spond to transient noise spikes on v cc that cross into the deselect window during the time the de- vice is sampling v cc . therefore, decoupling of the power supply lines is recommended. when v cc drops below v so , the control circuit switches power to the internal battery, preserving data. the internal energy source will maintain data in the m48z129y/v for an accumulated period of at least 10 years at room temperature. as system power rises above v so , the battery is disconnect- ed, and the power supply is switched to external v cc . deselect continues for t rec after v cc reach- es v pfd (max). for more information on battery storage life refer to the application note an1012. figure 10. power down/up mode ac waveforms ai03610 v cc e outputs don't care high-z tf tfb tr trb valid valid recognized recognized v pfd (max) v pfd (min) v so trec rst (per control input) (per control input) twpt tdr
m48z129y*, m48z129v 12/17 table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 3. at 25c, v cc = 0v. symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time m48z129y 10 s m48z129v 150 t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t wpt write protect time m48z129y 40 150 s m48z129v 40 250 t rec v pfd (max) to rst high 40 200 ms symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48z129y 4.2 4.35 4.5 v m48z129v 2.7 2.9 3.0 v v so battery back-up switchover voltage m48z129y 3.0 v m48z129v 2.45 v t dr (3) expected data retention time 10 years
13/17 m48z129y*, m48z129v v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 11) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 11. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
m48z129y*, m48z129v 14/17 package mechanical information figure 12. pmdip32 C 32-pin plastic module dip, package outline note: drawing is not to scale. table 11. pmdip32 C 32-pin plastic dip, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 C 0.015 C b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n32 32 pmdip a1 a l be1 d e n 1 ea e3 s c
15/17 m48z129y*, m48z129v part numbering table 12. ordering information scheme note: 1. contact local sales office for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. example: m48z 129y C70 pm 1 tr device type m48z supply voltage and write protect voltage 129y (1) = v cc = 4.5 to 5.5v; 4.2v v pfd 4.5v 129v = v cc = 3.0 to 3.6v; 2.7v v pfd 3.0v speed C70 = 70ns (m48z129y) C85 = 85ns (m48z129v) package pm = pmdip32 temperature range 1 = 0 to 70c shipping method blank = tubes tr = tape & reel
m48z129y*, m48z129v 16/17 revision history table 13. document revision history date rev. # revision details december 1999 1.0 first issue 30-mar-00 2.0 from preliminary data to data sheet 20-jun-00 2.1 t glqx changed for m48z129y (table 7) 14-sep-01 3.0 reformatted; temperature information added to tables (table 4, 5, 7, 8, 9, 10) 29-may-02 3.1 add countries to disclaimer 02-apr-03 4.0 v2.2 template applied; test condition updated (table 10)
17/17 m48z129y*, m48z129v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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